Yield (Circuit)

Yield is a critical metric in integrated circuit (IC) reliability engineering, measuring the proportion of manufactured chips that meet specified performance and functional requirements. These specifications may include timing, power, area, and noise margins, among others. Despite highly controlled manufacturing processes, inherent variability in semiconductor fabrication can cause deviations that affect final circuit behavior.

In modern semiconductor production, yield directly influences manufacturing cost and product viability. High yield means more functional chips per wafer, reducing cost per chip and maximizing economic return. Conversely, low yield leads to increased waste, reduced throughput, and higher production costs, especially in advanced process nodes such as 7nm and below, where each wafer represents a significant financial investment.

To mitigate these risks, circuit designers must address yield proactively during the design phase. This involves not only estimating the yield under expected process variations but also optimizing the design to make it more robust. Yield considerations are now an integral part of electronic design automation (EDA) workflows, where simulation and optimization tools help engineers navigate the complex trade-offs between performance, area, power, and manufacturability.

Consequently, two key challenges arise in yield-centric design: yield estimation (also referred to as yield analysis), which seeks to accurately compute the probability of a circuit meeting specifications under variation; and yield optimization, which aims to adjust design parameters to improve this probability. Both tasks are essential for ensuring that designs are both functional and cost-effective in real-world fabrication.

Background

As semiconductor technology advances into nanometer scales, integrated circuits become increasingly sensitive to process-induced variability. The manufacturing of ICs involves numerous steps—such as photolithography, etching, doping, and deposition—each of which introduces variability at different scales. These variations manifest both globally (across wafers or dies) and locally (within a single die), influencing critical electrical parameters such as threshold voltage, channel length, oxide thickness, and mobility.

One key source of variability is random dopant fluctuation (RDF), where the discrete and stochastic nature of dopant atoms in the transistor channel leads to unpredictable threshold voltage shifts. Similarly, line-edge roughness (LER) causes variations in transistor gate dimensions, further affecting drive strength and switching speed. Other contributors include oxide thickness variations, work-function fluctuations, and stress-induced mobility changes.

These variations are especially consequential for analog and mixed-signal circuits, where performance often hinges on precise matching of components and predictable analog behavior. For example, mismatch in current mirrors or differential pairs can lead to significant gain errors or offset voltages, degrading circuit accuracy. Moreover, high-speed or high-frequency circuits—such as those in RF applications—are vulnerable to parasitic variation and layout-dependent effects, making yield degradation even more pronounced.

In digital designs, process variations can lead to timing violations, increased leakage currents, or reduced noise margins, particularly in timing-critical paths. For memory circuits like SRAM, variation-induced read/write failures and access time degradation are well-documented challenges. As a result, ensuring that circuits perform correctly under these variations is a central concern across all IC domains.

To capture the statistical nature of these effects, yield is defined as the probability that a circuit, fabricated under such variations, satisfies all performance constraints. This probabilistic view allows designers to analyze how process variability translates into performance uncertainty, and how often these uncertainties push a design outside of acceptable limits.

As variability continues to grow with each process node, the challenge of maintaining high yield becomes more complex. Addressing this challenge requires close collaboration between technology developers, circuit designers, and EDA tool providers to develop models, methodologies, and algorithms that can accurately predict, analyze, and mitigate the impact of process variations throughout the IC design and fabrication pipeline.

Formulation

Formal definition of yield (or failure rate): From a geometric perspective, failure rate estimation essentially corresponds to computing the area of the circuit performance surface that lies above the threshold. However, since circuit performance can only be evaluated via simulation, there is no explicit analytical expression for it.

This section presents a formal definition of circuit yield. Let, $\mathbf {x} =[x_{1},x_{2},\cdots ,x_{d_{x}}]^{T}\in {\mathcal {X}}$ denote design parameters (e.g. length and width of a transistor) which are controlled by designer, where ${\mathcal {X}}$ defines the feasible design space. And the manufacturing process variations are assumed fully captured by the random variables $\mathbf {v} =[v_{1},v_{2},\cdots ,v_{d_{v}}]^{T}\in {\mathcal {V}}$. Without loss of generality, variational parameters (also referred as process parameters) are often modeled as a standard normal distribution:

$p(\mathbf {v} )={\frac {1}{(2\pi )^{d/2}}}\exp \left(-{\frac {1}{2}}\mathbf {v} ^{\top }\mathbf {v} \right)$

Circuit performance $m_{k}$ is determined by both design and variation parameters, and can be modeled as a deterministic function $z_{k}=f_{k}(\mathbf {x} ,\mathbf {v} )$. If all performance specifications are satisfied, the circuit is considered qualified. To formalize this, an indicator function is defined to determine whether a given circuit instance meets all required specifications:

$I(\mathbf {x} ,\mathbf {v} )={\begin{cases}1&{\text{if }}z_{k}\leq z_{k}^{0}{\text{ for all }}k\\0&{\text{otherwise}}\end{cases}}$

where $z_{k}^{0}$ is the $k$-th performance specification. For a given design $\mathbf {x}$, yield is defined as the probability that a manufactured circuit meets all design specifications under process variations, which is mathematically formalized as:

$g(\mathbf {x} )\triangleq \mathbb {E} (I(\mathbf {x} ,\mathbf {v} ))=\int _{\mathcal {V}}I(\mathbf {x} ,\mathbf {v} )p(\mathbf {v} )d\mathbf {v}$

In some literature, for convenience, failure rate $P_{f}(\mathbf {x} )$ is often used as an equivalent representation of yield ($P_{f}(\mathbf {x} )+g(\mathbf {x} )=1$).

Yield estimation

The yield estimation problem concerns how to accurately estimate the yield value $g(\mathbf {x} )$ with minimal simulation cost, especially for high-dimensional circuits. The main challenge lies in the fact that $f_{k}(\mathbf {x} ,\mathbf {v} )$ can only be evaluated through time-consuming circuit simulations. As a result, the yield function $g(\mathbf {v} )$ does not have a closed-form expression and must be estimated using numerical methods.

Currently, the industrial gold standard for yield estimation is the Monte Carlo method (MC), which approximates the yield as:

$g(\mathbf {x} )\approx {\frac {1}{N}}\sum _{i=1}^{N}I(\mathbf {x} ,\mathbf {v} _{i})$

where $\{\mathbf {v} _{i}\}_{i=1}^{N}$ are independent and identically distributed samples drawn from the distribution $p(\mathbf {v} )$. The major drawback of the MC method lies in its inefficiency. In practice, yield targets are often extremely high, leading to a rare-event setting where only a small subset of samples violate the specifications. Consequently, a large number of simulations is required to achieve statistically accurate yield estimates. For example, estimating a failure rate of $10^{-5}$ requires approximately $10^{7}$ simulations for 10% relative error, which may take several hours.

To improve the efficiency of yield estimation, one can either reduce the number of required simulations or lower the cost of each simulation. These two strategies correspond to two major classes of optimization techniques: importance sampling and surrogate modeling, respectively.

Comparison between Importance Sampling and Monte Carlo:Monte Carlo sampling draws random samples from the entire space of variational parameters according to a standard normal distribution. In contrast, importance sampling generates samples from a proposal distribution that is biased toward the failure region, thereby improving the efficiency of yield estimation.

Importance sampling (IS) is a statistical technique used to improve the efficiency of Monte Carlo simulations, particularly in rare-event scenarios where standard sampling would require an impractically large number of evaluations. In the context of yield estimation, IS focuses computational resources on the failure region—the set of process variation instances that cause a circuit to violate specifications—which is otherwise sparsely represented under normal distributions.

Instead of sampling from the original probability distribution of process variations (typically a standard normal), IS introduces a proposal distribution that over-samples the critical or rare regions. The estimator then corrects for this bias using a likelihood ratio, ensuring that the final yield estimate remains unbiased.

Mathematically, importance sampling can be expressed as:

$g(\mathbf {x} )=\int _{\mathcal {V}}I(\mathbf {x} ,\mathbf {v} )p(\mathbf {v} )d\mathbf {v} =\int _{\mathcal {V}}I(\mathbf {x} ,\mathbf {v} ){\frac {p(\mathbf {v} )}{q(\mathbf {v} )}}q(\mathbf {v} )d\mathbf {v} \approx {\frac {1}{M}}\sum _{i=1}^{M}I(\mathbf {x} ,\mathbf {v} '_{i}){\frac {p(\mathbf {v} '_{i})}{q(\mathbf {v} '_{i})}}$

where $\{\mathbf {v} _{i}'\}_{i=1}^{M}$ are independent and identically distributed samples drawn from the distribution $q(\mathbf {v} )$. By carefully designing the suitable proposal distribution $q(\mathbf {v} )$, importance sampling can obtain sufficient failure samples with significantly fewer simulations, enabling accurate yield estimation ($M\ll N$).

The key challenge in IS is choosing a good proposal distribution $q(\mathbf {v} )$. An ideal $q(\mathbf {v} )$ would concentrate samples in the failure region without entirely neglecting other feasible domains, thereby balancing variance reduction with estimator accuracy. Poorly chosen $q(\mathbf {v} )$ can lead to high variance or numerical instability due to large likelihood ratios.

Surrogate modeling employs data-driven machine learning techniques to approximate the behavior of computationally expensive circuit simulators. The key idea is to learn a predictive model that maps input design and process parameters to output performance metrics, mimicking the true simulator with much lower evaluation cost.

Once trained to a sufficient level of accuracy, the surrogate model can be used as a drop-in replacement for the original simulator in yield estimation workflows. This substitution drastically reduces the number of high-fidelity simulations required, making it possible to perform large-scale statistical analysis, optimization, and sensitivity studies within reasonable computational budgets.

Surrogate modeling is especially beneficial in high-dimensional design spaces or when the simulation time per sample is prohibitively high. It enables rapid exploration of the design space and supports iterative processes such as Bayesian optimization and adaptive sampling.

Common surrogate models include Gaussian processes (GP), conditional normalizing flows (CNF), low-rank tensor approximations, Bayesian neural networks, and radial basis function networks.

These approaches enable more efficient use of simulation budgets, especially in high-dimensional or compute-intensive scenarios, and form the foundation for scalable yield-aware design methodologies.

Yield optimization

While accurate yield estimation is critical, the ultimate objective for circuit designers is to optimize yield—that is, to find a design configuration that maximizes the probability of meeting performance specifications under process variations. Yield optimization balances two competing goals: maximizing the statistical success rate (yield) and minimizing the computational cost associated with evaluating different design candidates.

Formally, yield optimization can be posed as the following optimization problem:

  $\mathbf {x} ^{*}=\arg \max _{\mathbf {x} \in {\mathcal {X}}}g(\mathbf {x} )$

where $g(\mathbf {x} )$ denotes the yield function corresponding to design $\mathbf {x}$ , and ${\mathcal {X}}$ is the feasible design space.

A major challenge in this formulation is that $g(\mathbf {x} )$ has no closed-form expression. Evaluating $g(\mathbf {x} )$ for any given design point requires computationally intensive simulations—often via Monte Carlo methods or their advanced variants. Furthermore, the yield function is generally non-convex, non-smooth, and lacks gradient information, making traditional gradient-based optimization algorithms inapplicable.

To address this, yield optimization is often treated as a black-box optimization problem, where the objective function can only be accessed through function evaluations (i.e., simulations). Among black-box methods, Bayesian optimization (BO) has become particularly prominent due to its sample efficiency.

In Bayesian yield optimization, a Gaussian Process (GP) model is used as a surrogate to approximate the unknown yield function. This model captures both predictions and associated uncertainty. At each iteration, an acquisition function—such as Expected Improvement (EI) or Upper Confidence Bound (UCB)—is optimized to select the next design point. The selected point is then evaluated using a yield estimation method, and the GP model is updated with the new data. This process is repeated iteratively until a satisfactory yield is achieved or the simulation budget is exhausted.

This framework enables designers to navigate complex, high-dimensional design spaces with relatively few expensive evaluations. In addition to Bayesian methods, alternative black-box algorithms—such as Differential Evolution (DE)—have also been explored for yield optimization, especially in cases where model assumptions for Bayesian methods do not hold or evaluation noise is high.

As circuit designs continue to grow in complexity and variability, efficient yield optimization remains a vital component of design automation, bridging the gap between theoretical robustness and practical manufacturability.

Some Existing Works

Yield Estimation

Importance Sampling

Minimum-norm importance sampling (MNIS) proposes a highly efficient technique specifically designed for rare-event analysis in memory circuits, particularly 6T-SRAM. It introduces a norm minimization principle inspired by Large Deviation Theory to construct an effective proposal distribution for IS, achieving massive speedups over standard Monte Carlo simulation while maintaining high accuracy.

Scaled-sigma sampling (SSS) accelerates rare-event analysis by amplifying process variations to increase failure rates during simulation. Failure probabilities under nominal conditions are then inferred through statistical extrapolation. By avoiding direct sampling in low-probability regions, SSS significantly reduces simulation cost while maintaining accuracy.

Hyperspherical Clustering and Sampling (HSCS) is a method combining hyperspherical presampling with clustering to identify multiple failure regions. It builds mixture IS distributions based on spherical exploration of the parametric space. HSCS is shown to be more robust than prior methods in covering disjoint failure regions, providing accurate yield estimation with high sample efficiency.

Adaptive Importance Sampling (AIS) proposes an adaptive method to address the challenge of estimating extremely low failure probabilities in memory circuits. Unlike static IS methods, AIS iteratively updates the sampling distribution by resampling weighted failure samples, improving both efficiency and robustness. It significantly outperforms traditional methods in both single and multiple failure region scenarios, achieving over 4000× speedup in complex circuits.

Adaptive clustering and sampling (ACS) addresses multi-modal failure analysis by clustering observed failures and constructing a weighted Gaussian mixture for guided sampling. The method adaptively explores cone-shaped subspaces, achieving high sample efficiency and outperforming conventional techniques in high-dimensional settings, such as 576-dimensional SRAM circuits.

Every failure is a lesson (EFIAL) enhances minimum-norm importance sampling by incorporating all observed failure samples instead of relying solely on the closest one. The resulting proposal distribution is tuning-free and scales linearly with the number of failures. EFIAL yields up to 13.5× speedup and notable accuracy improvements, especially when combined with pre-sampling techniques such as onion sampling.

Variational importance sampling (VIS) formulates yield estimation as a variational optimization problem. Unlike traditional norm-based methods, VIS places the optimal mean shift vector beyond the failure boundary and employs full-covariance models, skew-normal distributions, and mixture models for multi-modal failures. These refinements enable up to 29× speedup and improved accuracy in rare-event estimation.

Surrogate modeling

Low-Rank Tensor Approximation is a technique for representing high-dimensional functions using a compact sum of low-rank components. It reduces computational complexity by capturing key patterns with fewer parameters, making it efficient for modeling problems with many input variables. Low-rank tensor approximation-based yield estimation (LRTA) constructs a sparse polynomial surrogate using tensor decomposition to model high-dimensional circuit performance. An adaptive sampling strategy focuses training near failure regions, enabling accurate yield estimation with up to 6300× speedup over Monte Carlo, even in dimensions as high as 597.

Convolutional-entropy-based active learning technique proposed in BYA: exploration and exploitation for yield decision margins.

Gaussian Process (GP) is a non-parametric regression model that defines a distribution over functions, where any finite set of input points has a joint Gaussian distribution. It provides both predictive means and uncertainty estimates, making it well-suited for modeling complex systems with limited data and guiding adaptive sampling. Bayesian yield analysis (BYA) uses independent Gaussian processes to model circuit performance metrics and applies a Bernoulli link function to convert outputs into pass/fail probabilities. An entropy-based acquisition function selects new samples that most reduce predictive uncertainty, enabling accurate and efficient yield estimation in high-dimensional spaces. Adaptive Shrinkage Deep Kernel Learning (ASDK) combines deep kernel Gaussian processes with a shrinkage-based feature selection mechanism to identify dominant process variables. The surrogate is refined through entropy-based sampling near failure boundaries, allowing scalable and accurate yield estimation in problems with hundreds of dimensions.

Bayesian Neural Network (BNN) is a probabilistic extension of standard neural networks that introduces uncertainty by treating weights and biases as random variables with prior distributions. This enables it to model predictive uncertainty and prevent overfitting, making it suitable for surrogate modeling in data-scarce, high-dimensional settings. Bayesian Neural Network-based yield estimation (BNN-YE) constructs a global surrogate model of circuit performance using a Bayesian neural network trained on a small number of SPICE simulations. It estimates yield by running Monte Carlo on the trained surrogate, eliminating the need for additional simulations. The method achieves high accuracy with strong generalization due to the regularization effect of Bayesian inference, providing up to 100× speedup over standard Monte Carlo in SRAM yield estimation.

Surrogate modeling + Importance Sampling

Some methods combine surrogate modeling with importance sampling, using a learned surrogate to replace expensive SPICE simulations and designing proposal distributions to guide sampling. Yield is then estimated efficiently through importance sampling based on the surrogate.

Radial Basis Function Network (RBF) is a type of feedforward neural network that uses radial basis functions (typically Gaussian) as activation functions in the hidden layer. It is well-suited for interpolation tasks, offering smooth approximations of complex functions with relatively simple training and fast evaluation. Adaptive  Online Surrogate Modeling (AOSM) combines radial basis function networks with importance sampling to accelerate yield estimation. At each iteration, only the most informative sample—typically the current minimum-norm failure—is used to update the surrogate model. This surrogate then replaces SPICE simulations in subsequent importance sampling steps, achieving high efficiency with minimal training cost and preserving accuracy in rare-event estimation.

Yield Optimization

Adaptive Bayesian Yield Optimization (ABYO) formulates yield maximization as a Bayesian optimization problem. It leverages Gaussian processes and expected improvement for efficient sampling, and introduces a two-stage Monte Carlo estimator to adaptively allocate computational effort. This approach achieves up to 8× speedup while preserving accuracy in analog and SRAM circuit yield optimization.

Adaptive Online Surrogate Modeling (AOSM) accelerates SRAM yield optimization by combining population-based optimization with online-trained surrogate models. Building on efficient yield estimation, AOSM searches for high-yield designs via two-norm optimization of the optimal mean-shift vector and adaptively refines surrogate accuracy near optimal candidates. This achieves up to 150× speedup, enabling fully automatic and robust SRAM yield optimization within hours.

Bayesian Yield Analysis with Bayesian Optimization (BYA-BO) accelerates yield optimization by leveraging an efficient Bayesian yield estimation framework. Building on accurate and uncertainty-aware yield estimation, BYA-BO uses active learning and a unified Bayesian surrogate to rapidly identify high-yield designs. This approach achieves up to 5× speedup over previous state-of-the-art methods in SRAM and adder circuit optimization.

Kernel Density Estimation-based Bayesian Optimization (KDE-BO) reframes high-sigma yield estimation as a surrogate-guided importance sampling task. It combines Gaussian process surrogates with kernel density estimation (KDE) to construct accurate importance distributions, and adaptively refines both models during optimization. This approach enables over 100× speedup while maintaining accuracy in high-sigma yield analysis and design.

Max-value Entropy Search-based Bayesian Optimization (MES-BO) accelerates yield optimization by leveraging accurate, uncertainty-aware Bayesian yield estimation. Building on efficient yield estimation with Gaussian process regression, MES introduces an information-theoretic acquisition function to better explore the design space, reducing simulation cost while achieving robust high-yield designs for analog and SRAM circuits.

Optimal Proposal Transfer (OPT) formulates yield optimization as a proposal distribution transfer problem. OPT leverages conditional normalizing flows to transfer optimal proposals between designs, achieving robust and efficient yield estimation without surrogate models. This enables up to 12× speedup and consistent high-yield results on analog and SRAM circuits. The paper was nominated for Best Paper at the 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD).

Bayesian Neural Network-based Yield Optimization (BNN-YO) accelerates yield optimization by first constructing an accurate Bayesian neural network surrogate for yield estimation. Building on this foundation, BNN-YEO employs a smooth indicator approximation to enable efficient, gradient-based search for high-yield circuit designs. This approach achieves up to 20× speedup over previous methods in SRAM yield optimization, while effectively preventing overfitting.

See also

• Monte Carlo method
• Importance sampling
• Surrogate model
• Gaussian process
• Bayesian optimization