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Draft:Co-Design Automation

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Co-Design Automation, Inc.
Company typePrivate
IndustryElectronic design automation
Founded1997
FoundersSimon Davidmann, Peter Flake
DefunctSeptember 2002
FateAcquired by Synopsys
Key people
Simon Davidmann (CEO), Peter Flake (CTO), Phil Moorby (Chief Scientist)
ProductsSuperlog, Systemsim, Systemex

Co‑Design Automation, Inc. was a privately‑held American EDA software company established in 1997. It created the Superlog hardware description language (HDL) and two associated EDA tools, Systemsim and Systemex.[1] Elements of Superlog were later adopted by the industry and became part of the IEEE‑standard SystemVerilog language.[2] Co‑Design was acquired by Synopsys for approximately US $36 million in September 2002.[3]

History

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Founding and early development (1997–1999)

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Co‑Design was founded in 1997 by former HDL researchers Simon Davidmann and Peter Flake who had previously worked together on HILO, with offices in San Jose, California, and in Oxfordshire, England[1].

The company's objective was to develop a single language and tool flow that could bridge system specification, RTL design and functional verification.[4] This effort culminated in Superlog, first unveiled to the trade press in May 1999.[5]

In September 1999 Co‑Design withdrew Superlog from consideration by the OVI architecture committee for new languages, citing the need to control language evolution while commercial tools were still under development.[6]

Product releases and market reception (2000–2001)

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In January 2000 EE Times reported that Co‑Design recruited Phil Moorby, inventor of the Verilog language, as its chief scientist to "refine Superlog and move it toward standardization".[7]

Co‑Design introduced Systemsim in May 2000 as the first verification environment to allow efficient mixed simulation between SystemC and other design languages.[8] Coverage of the launch noted the tool's ability to co‑simulate C/C++, Verilog, and Superlog in a single kernel and introduced the CBlend technology which later evolved into the SystemVerilog DPI[8].

Early third‑party synthesis and customer uptake were reported in January 2001,[9] when Get2Chip (later acquired by Cadence) added Superlog support to its Volare architectural synthesis tool.[10] EE Times described the step as "strengthen[ing] Superlog's bid to become the next‑generation design language".[11]

Acquisition by Synopsys (2002)

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On 28 August 2002 Synopsys announced that it would acquire Co‑Design Automation for approximately US $36 million in cash and stock.[12] Synopsys' CEO Aart de Geus commented: "Co-Design Automation assembled many of the world's leading Verilog language experts to deliver Superlog technology. Having technology pioneers such as Phil Moorby, Peter Flake and Simon Davidmann join our team of verification experts significantly accelerates our Smart Verification strategy"[12].

Trade‑press analysis positioned the deal as a move by Synopsys to fold Superlog technology into its own Verilog simulator and to bolster its high‑level design strategy.[13]

Products

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Superlog – a superset of Verilog that added C‑like syntax, object‑oriented constructs, verification capabilities and early assertion support.[14][15]

Systemsim – a mixed‑language simulator supporting Superlog, Verilog, and C.[16]

Systemex – a system‑to‑RTL design extractor that generated synthesizable Verilog HDL from higher‑level Superlog models[16].

Legacy and influence

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Although Superlog itself never achieved wide commercial adoption, many of its language constructs were incorporated into the Accellera SystemVerilog proposal in 2002 and subsequently into the IEEE 1800 standard[14]. Modern EDA methodologies rely on object-oriented test‑bench coding and assertion‑based verification - features traceable to Superlog's original design.[17][18]

Co‑Design's chief scientist Phil Moorby was recognized for his language work beyond the company: he received the industry's Phil Kaufman Award in 2005 for Verilog[19] and was named a Computer History Museum Fellow in 2016.[20]

References

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  1. ^ a b Clarke, Peter (1999-05-31). "Startup to field next-generation design language". EE Times. Retrieved 2025-07-11.
  2. ^ "IEEE Standards Association". IEEE Standards Association. Retrieved 2025-07-11.
  3. ^ EETimes (2002-08-28). "Synopsys snaps up Co-Design for Superlog language". EE Times. Retrieved 2025-07-11.
  4. ^ "Co-Design Automation Launches Innovative Product Line to Reshape System Design Methodologies". www.design-reuse.com. Retrieved 2025-07-11.
  5. ^ Clarke, Peter (1999-05-31). "Startup to field next-generation design language". EE Times. Retrieved 2025-07-11.
  6. ^ Goering, Richard (1999-09-14). "Co-Design pulls Superlog from OVI consideration". EE Times. Retrieved 2025-07-11.
  7. ^ Santarini, Michael (2000-01-17). "Verilog creator joins tool startup". EE Times. Retrieved 2025-07-11.
  8. ^ a b EETimes (2000-05-08). "Co-Design Provides Open System Verification Environment". Retrieved 2025-07-11.
  9. ^ Cooley, John (2000-11-06). "The Superlog evolution". EE Times. Retrieved 2025-07-11.
  10. ^ Goering, Richard (2001-02-02). "Demo eases Superlog into the public eye". EDN. Retrieved 2025-07-11.
  11. ^ EETimes (2001-01-22). "Superlog design language picks up speed". EE Times. Retrieved 2025-07-11.
  12. ^ a b "Synopsys Acquires Co-Design Automation to Accelerate Delivery of Next-Generation HDL With SUPERLOG Technology". www.design-reuse.com. Retrieved 2025-07-11.
  13. ^ EETimes (2002-08-28). "Synopsys snaps up Co-Design for Superlog language". EE Times. Retrieved 2025-07-11.
  14. ^ a b Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337.
  15. ^ Flake, Peter L.; Davidmann, Simon J. (2000-01-28). "Superlog, a unified design language for system-on-chip". Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00. New York, NY, USA: Association for Computing Machinery. pp. 583–586. doi:10.1145/368434.368814. ISBN 978-0-7803-5974-1.
  16. ^ a b "Imperas Reunites with SystemVerilog Co-Founders at DVCon 2021". Electronic Design. 2021-02-25. Retrieved 2025-07-11.
  17. ^ "SystemVerilog for Design". SpringerLink. 2006. doi:10.1007/0-387-36495-1. ISBN 978-0-387-33399-1.
  18. ^ Dettmer, R. (2004-08-01). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803 (inactive 12 July 2025).{{cite journal}}: CS1 maint: DOI inactive as of July 2025 (link)
  19. ^ Newton, Richard. "Phil Moorby: Phil Kaufman Award, 2005". people.eecs.berkeley.edu. Retrieved 2025-07-11.
  20. ^ "Philip Moorby". CHM. 2025-08-07. Retrieved 2025-07-11.
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